1. Technical Field
Embodiments relate to a flash memory device. More particularly, embodiments relate to a flash memory device configured to prevent a soft program effect during a read operation.
2. Description of the Related Art
In general, a flash memory device is a type of an EEPROM wherein a plurality of memory regions are programmed or erased by a single program or erase operation. As the EEPROM is able to be electrically erased and programmed, it is widely applied in system programming and in supplementary memory devices. Particularly, a flash EEPROM (also referred to herein as a “flash memory”) has advantages when applied as a large-capacity supplementary memory device because the flash EEPROM may be more highly integrated than a conventional EEPROM. A flash memory device may be classified as a NAND flash memory device or a NOR flash memory device depending on the form of logic gate. Generally, the NAND flash memory device is more highly-integrated than the NOR flash memory device.
FIG. 1 illustrates a block diagram of a NAND flash memory device 10. Referring to FIG. 1, the NAND flash memory device 10 may include a memory cell array 20, a row selection circuit 40 (identified as “X-SEL” in FIG. 1), and a page buffer circuit 60.
The memory cell array 20 may include a plurality of cell strings 21, i.e., NAND strings, each connected to corresponding bit lines BL0 to BLm-1. The cell string 21 of each column may include a string selection transistor SST as a first selection transistor, a ground selection transistor GST as a second selection transistor, and a plurality of flash EEPROM cells, i.e., memory cells, MC0 to MCn-1 connected in series between the selection transistors SST and GST. The string selection transistor SST of each column may have a gate connected to a string selection line SSL and a drain connected to a corresponding bit line. The ground selection transistor GST may have a source connected to a common source line CSL and a gate connected to the ground selection line GSL. The memory cells MCn-1 to MC0 may be connected in series between the source of the string selection transistor SST and the drain of the ground selection transistor GST. The cells of each cell string may consist of floating gate transistors whose control gates are connected to corresponding word lines WLn-1 to WL0, respectively. The string selection line SSL, the word lines WL0 to WLn-1, and the ground selection line GSL may be electrically connected to the row selection circuit 40. The bit lines BL0 to BLm-1 arranged on the memory cell array 20 may be electrically connected to the page buffer circuit 60.
The row selection circuit 40 may select one word line from among the word lines WL0 to WLn-1 according to the row address information, and may provide word line voltages to selected and unselected word lines according to each mode of operation, respectively. For example, the row selection circuit 40 may supply a program voltage to a selected word line and supply a pass voltage to unselected word lines during a program mode of operation. The page buffer circuit 60 may supply a power voltage, i.e., a program-inhibited voltage, or a ground voltage, i.e., a program voltage, to the bit lines BL0 to BLm-1 respectively, according to data to be programmed during a program mode of operation. Memory cells of the NAND flash memory 10 may be erased and programmed by using a Fowler-Nordheim tunneling current. During a read mode of operation, i.e., a read operation, the row selection circuit 40 may supply a ground voltage GND to a selected word line, and may supply a read voltage to unselected word lines.
The page buffer circuit 60 may recognize data transferred from memory cells of the selected word line by means of the bit lines BL0 to BLm-1 during a read/verification mode of operation. Through the recognition operation of the page buffer circuit 60, it may be determined whether the memory cell is a programmed cell or an erased cell.
The read mode of operation may include bit line discharge, bit line precharge, bit line development, and sensing intervals, in that order. Bit lines may be discharged during the bit line discharge interval. The discharged bit lines may be precharged during the bit line precharge interval so as to have a predetermined precharge level. Also, after the bit lines are discharged, during the bit line precharge interval, a read voltage Vread (e.g. +4.5V) may be applied to the unselected word lines and 0V may be supplied to the selected word line. During the bit line development interval, where the memory cell connected to the selected word line is an erased cell, i.e., an on-cell, the precharge level of the bit line may fall to a low level, e.g., a ground level. However, if the memory cell is a programmed cell, i.e., an off-cell, the precharge level of the bit line may be maintained. Likewise, the precharge levels of the bit lines may vary according to the program state of the memory cells, which is called a bit line development. The precharge levels of the bit lines may be sensed during the sensing interval by the page buffer circuit 60. Through this read operation, it may be determined whether a memory cell is an erased cell or a programmed cell.
During a read mode of operation, when a read voltage is supplied to the string selection line SSL or the ground selection line GSL during a bit line development interval, a word line adjacent to the string selection line SSL or adjacent to the ground selection line GSL may have a higher voltage than the read voltage as a result of a coupling effect. In this case, the cells connected to the word line adjacent to the string selection line SSL or adjacent to the ground selection line GSL may be undesirably soft programmed.